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MC74VHC541 Octal Bus Buffer
The MC74VHC541 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC541 is a noninverting type. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
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20 1
SOIC-20WB SUFFIX DW CASE 751D
* * * * * * * * * * * *
High Speed: tPD = 3.7ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 5.5 V Operating Range Low Noise: VOLP = 1.2 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 134 FETs or 33.5 Equivalent Gates Pb-Free Packages are Available*
A1 A2 A3 DATA INPUTS A4 A5 A6 A7 A8 OUTPUT ENABLES OE1 OE2 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 NONINVERTING OUTPUTS
20
TSSOP-20 SUFFIX DT CASE 948E 1
20 1
SOEIAJ-20 SUFFIX M CASE 967
PIN ASSIGNMENT
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
FUNCTION TABLE
Inputs Output Y OE1 OE2 L L X H A L H X X L H Z Z L L H X
Y8
ORDERING INFORMATION Figure 1. Logic Diagram
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 4 of this data sheet.
1
April, 2006 - Rev. 5
Publication Order Number: MC74VHC541/D
MC74VHC541
I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I III II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I III II II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II II II II I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I III II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I II I I I I I I II IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIII II IIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III II I I I II I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII I IIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I I I III I I IIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I III I I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III III I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I
II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III III II I II II I I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
VCC Vin SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage DC Input Voltage Value Unit V V V - 0.5 to + 7.0 - 0.5 to + 7.0 Vout IIK DC Output Voltage - 0.5 to VCC + 0.5 - 20 20 25 50 500 450 Input Diode Current mA mA mA mA IOK Iout Output Diode Current DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature SOIC Packages TSSOP Package mW _C Tstg - 65 to + 150 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin Parameter DC Supply Voltage DC Input Voltage
Min 2.0 0 0
Max 5.5 5.5
Unit V V V
Vout TA
DC Output Voltage
VCC
Operating Temperature, All Package Types Input Rise and Fall Time VCC = 5.0V 0.5V
- 40 0 0
+ 85 100 20
_C
tr, tf
VCC = 3.3V 0.3V
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL Parameter
Test Conditions
VCC V
TA = 25C Typ
TA = - 40 to 85C Min Max
Min
Max
Unit V V V
Minimum High-Level Input Voltage
2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5
1.50 VCC x 0.7
1.50 VCC x 0.7
Maximum Low-Level Input Voltage
0.50 VCC x 0.3
0.50 VCC x 0.3
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL IOH = - 50mA
1.9 2.9 4.4
2.0 3.0 4.5
1.9 2.9 4.4
Vin = VIH or VIL IOH = - 4mA IOH = - 8mA Vin = VIH or VIL IOL = 50mA
2.58 3.94
2.48 3.80
VOL
Maximum Low-Level Output Voltage
0.0 0.0 0.0
0.1 0.1 0.1
0.1 0.1 0.1
V
Vin = VIH or VIL IOL = 4mA IOL = 8mA
0.36 0.36
0.44 0.44
Iin
Maximum Input Leakage Current
Vin = 5.5V or GND
0 to 5.5 5.5 5.5
0.1
1.0 2.5 40.0
mA mA mA
IOZ
Maximum 3-State Leakage Current
Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND
0.25 4.0
ICC
Maximum Quiescent Supply Current
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MC74VHC541
I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIII I IIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIII I I IIII IIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I IIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I IIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII I I I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIII IIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII I IIII II I IIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII III I I IIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
Symbol tPLH, tPHL Parameter TA = 25C Typ 5.0 7.5 3.5 5.0 6.8 9.3 4.7 6.2 TA = - 40 to 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 8.5 12.0 6.0 8.0 Test Conditions Min Max Unit ns Maximum Propagation Delay, A to Y VCC = 3.3 0.3V VCC = 5.0 0.5V VCC = 3.3 0.3V RL = 1kW VCC = 5.0 0.5V RL = 1kW VCC = 3.3 0.3V RL = 1kW VCC = 5.0 0.5V RL = 1kW VCC = 3.3 0.3V (Note 1) VCC = 5.0 0.5V (Note 1) CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF 7.0 10.5 5.0 7.0 tPZL, tPZH Output Enable TIme, OE to Y 10.5 14.0 7.2 9.2 12.5 16.0 ns 8.5 10.5 tPLZ, tPHZ Output Disable Time, OE to Y 11.2 6.0 15.4 8.8 1.5 1.0 10 17.5 10.0 1.5 1.0 10 ns tOSLH, tOSHL Output to Output Skew ns ns Cin Maximum Input Capacitance 4 6 pF pF Cout Maximum Three-State Output Capacitance (Output in High Impedance State) Typical @ 25C, VCC = 5.0V 18 CPD Power Dissipation Capacitance (Note 2) pF 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25C Symbol VOLP VOLV VIHD VILD Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Parameter Typ 0.9 - 0.9 Max 1.2 - 1.2 3.5 1.5 Unit V V V V
SWITCHING WAVEFORMS
VCC VCC A tPLH 50% VCC Y 50% tPHL GND Y 50% VCC tPZH 50% VCC tPHZ VOH -0.3V HIGH IMPEDANCE VOL +0.3V OE1 or OE2 50% tPZL tPLZ 50% GND HIGH IMPEDANCE
Y
Figure 2.
Figure 3.
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MC74VHC541
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST OUTPUT TEST POINT 1kW C L* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
INPUT
Figure 6. Input Equivalent Circuit
ORDERING INFORMATION
Device MC74VHC541DWR2 MC74VHC541DWR2G MC74VHC541DT MC74VHC541DTG MC74VHC541DTR2 MC74VHC541DTR2G MC74VHC541MEL MC74VHC541MELG Package SOIC-20WB SOIC-20WB (Pb-Free) TSSOP-20* TSSOP-20* TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 1000 / Tape & Reel 1000 / Tape & Reel 75 Units / Rail 75 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 2000 / Tape & Reel 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
MARKING DIAGRAMS
SOIC-20WB 20 VHC541 AWLYYWWG 1 20 VHC 541 ALYWG G 1 TSSOP-20 20 74VHC541 AWLYWWG 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) SOEIAJ-20
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MC74VHC541
PACKAGE DIMENSIONS
SOIC-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B
20X
L
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
2X
L/2
20
11
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74VHC541
PACKAGE DIMENSIONS
SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE A
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
b 0.13 (0.005)
M
A1 0.10 (0.004)
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